1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device suitable to control the threshold value thereof for power reduction at standby time.
2. Description of the Prior Art
In general, one of the effective methods of reducing the power consumption of a semiconductor integrated circuit device including MOSFETs, in particular of a CMOS integrated circuit is to reduce the supply voltage thereof. When the supply voltage is reduced, however, the operating speed of the CMOS circuit inevitably decreases.
Therefore, when not only the supply voltage but also the threshold value are both reduced, it is possible to reduce the power consumption at operation time without decreasing the circuit operating speed. In this case, however, when the threshold value is reduced, since the subthreshold current of the MOSFET increases at standby time, the consumption power increases at standby time. Therefore, it is desirable to keep the threshold value high at standby time but low at operation time.
The threshold value of the MOSFET is modulated by the substrate potential (back gate effect). Therefore, when a bias voltage is applied to the substrate (a potential lower than the source is applied in an NMOS but a potential higher than the source is applied in a PMOS), the threshold value can be increased. Therefore, a technique for controlling the threshold value of the MOSFET by utilization of this phenomenon has been developed, as disclosed by a reference document 1: K. Seta, et al., "50% Active-Power Saving without Speed Degradation using Stand-by Power Reduction (SPR) Circuit" ISSCC Digest of Technical Papers, pp. 318-319, February, 1995.
FIG. 16 shows the construction of a threshold value control circuit as disclosed by this reference document 1, in which the threshold value is switched from the standby time to the operation time or vice versa. For instance, at standby time, -2V is applied to a P well or a P type substrate (referred to as a P-type semiconductor substrate), and 4V is applied to an N well or an N type substrate (referred to as an N-type semiconductor substrate). Further, at operation time, 0V is applied to the P-type semiconductor substrate and 2V is applied to the N-type semiconductor substrate.
In the above-mentioned circuit as shown in FIG. 16, however, two new supply voltages V.sub.PBB (=-2V) and V.sub.NBB (=4V) are necessary in addition to a drive supply voltage V.sub.DD (=-2V) and a ground supply voltage GND (=0V).
Further, in the circuit as shown in FIG. 16, the substrate terminal of an NMOSFET is connected to the supply voltage GND; the substrate terminal of another NMOSFET is connected to the supply voltage V.sub.PBB ; the substrate terminal of a PMOSFET is connected to the supply voltage V.sub.DD ; and the substrate terminal of another PMOSFET is connected to the supply voltage V.sub.NBB, so that a triple-well structure is required, thus causing a problem in that the manufacturing process inevitably increases.